1. Field of the Invention
The present invention relates to a constant-current generator and a differential amplifier which depend little upon a power source voltage, and a semiconductor integrated circuit which includes the differential amplifier.
2. Description of the Related Art
Semiconductor integrated circuits, such as microcomputers and DRAMs, have had their operating speeds heightened year by year. There has been developed, for example, an SDRAM (Synchronous DRAM) in which an input/output interfacing circuit is operated at high speed in synchronization with a clock signal, thereby to write/read data at high speed.
FIG. 1 shows an input buffer which is used in the semiconductor integrated circuit of this kind.
The input buffer 1 is constructed of a constant-current generator 2 including a bias part 2a and a driver part 2b, and a differential amplifier 3.
The bias part 2a is formed of a pMOS transistor 4, and a resistor 5 having a high resistance. The pMOS transistor 4 has its source connected to a power supply line VDD, and has its drain and gate connected to a node N1. The resistor 5 has its one end connected to the node N1, and has its other end connected to a ground line VSS. The driver part 2b is formed of a PMOS transistor 6. The pMOS transistor 6 has its source connected to the power supply line VDD, has its gate connected to the node N1, and has its drain connected to a node N2 being the common source of the differential amplifier 3. The PMOS transistors 4, 6 are formed having equal sizes at proximate positions, and the threshold voltages VT1 thereof are equalized. The constant-current generator 2 is constructed as a current mirror circuit.
The differential amplifier 3 includes a PMOS transistor 7a and an nMOS transistor 7b which are connected in series, and a PMOS transistor 8a and an nMOS transistor 8b which are also connected in series. Herein, a current mirror circuit is constructed of the transistors 7b, 8b. More specifically, the PMOS transistor 7a has its source connected to the node N2 and its drain connected to the drain and gate of the nMOS transistor 7b, and it receives an input signal VIN1 at its gate. The pMOS transistor 8a has its source connected to the node N2 and its drain connected to the drain of the nMOS transistor 8b, and it receives an input signal VIN2 at its gate. An output signal OUT is outputted from the common drain of the PMOS transistor 8a and the nMOS transistor 8b. The sources of the nMOS transistors 7b, 8b are connected to the ground line VSS.
Hereinbelow, the PMOS transistor and nMOS transistor shall be simply termed the xe2x80x9cpMOSxe2x80x9d and xe2x80x9cnMOSxe2x80x9d, respectively. In addition, the symbols VDD and VSS shall also denote a power supply voltage and a ground voltage, respectively.
FIG. 2 shows another input buffer 9.
The input buffer 9 is configured of a constant-current circuit 10 in which a current mirror circuit is constructed of nMOSs (nMOS transistors), and a differential amplifier 11 in which a current mirror circuit is constructed of pMOSs (PMOS transistors). The input buffer 9 is such a circuit that the pMOSs and nMOSs of the input buffer 1 are replaced with each other, and that the power supply voltage VDD and the ground voltage VSS are replaced with each other.
Next, the operation of the input buffer 1 will be explained. Complementary clock signals supplied from the exterior, for example, are applied as the input signals VIN1, VIN2 to the input buffer 1 shown in FIG. 1.
The bias part 2a of the constant-current generator 2 generates a predetermined voltage V1 at the node N1 by the action of the pMOS 4 and the resistor 5. Here, the resistance of the resistor 5 is set so that the voltage V1 may become a value xe2x80x9c(Power supply voltage VDD)xe2x88x92(Threshold voltage |VT1|)xe2x88x92-(Margin xcex1)xe2x80x9d. Thus, the pMOSs 4, 6 are reliably turned on owing to the margin xcex1.
A constant supply current IC is fed to the differential amplifier 3 by the turn-on operation of the PMOS 6. Here, the differential amplifier 3 is designed so that the voltage V2 of the node N2 may become smaller than a value xe2x80x9c(Power supply voltage VDD)xe2x88x92(Voltage V1)+(Threshold voltage |VT1|)xe2x80x9d. Therefore, the pMOS 6 operates in the saturation region of static characteristics as shown in FIG. 3. Accordingly, the supply current IC hardly changes even when the voltage V2 of the node N2 has changed to some extent under the influence of the operation of the differential amplifier 3.
As shown in FIG. 4, the differential amplifier 3 receives the input signals VIN1, VIN2 and outputs a differentially amplified signal as the output signal OUT.
Also in the input buffer 9 shown in FIG. 2, an operation similar to that of the input buffer 1 proceeds to differentially amplify input signals VIN1, VIN2 and to produce an output signal OUT.
Meanwhile, SDRAMs have recently become higher in the frequency of a clock signal. Further, with a DDR-SDRAM (Double Data Rate-Synchronous DRAM), data signals are inputted/outputted in synchronization with the respective rises of complementary clock signals. Therefore, in the SDRAM and the DDR-SDRAM, power supply noise is more liable to occur than in the conventional DRAM. Besides, the voltage drops due to increases in current which flows through power supply line and ground line. In consequence, a power supply voltage VDD and a ground voltage VSS are liable to shift. Concretely, the power supply voltage VDD and the ground voltage VSS respectively differ at distant positions within a chip.
By way of example, in a case where the ground voltage VSS has shifted toward a plus side in the input buffer 1 shown in FIG. 1, the voltage V1 of the node N1 rises as indicated by a broken line in FIG. 4. The supply current IC which is fed to the differential amplifier 3 decreases due to the rise of the voltage V1, so that the speed of the differential amplification of the input signals VIN1, VIN2 lowers. This results in the problem that the output timing of the output signal OUT lags as indicated by a broken line.
On the other hand, in a case where the ground voltage VSS has shifted toward a minus side, the voltage V1 of the node N1 falls as indicated by a dot-and-dash line. The supply current IC which is fed to the differential amplifier 3 increases due to the fall of the voltage V1. This incurs the problem that the output timing of the output signal OUT advances as indicated by a dot-and-dash line.
As a result, the timing margin of the circuitry narrows to make the timing design thereof difficult.
Also in the input buffer 9 shown in FIG. 2, when the power supply voltage VDD has shifted, problems similar to the above occur to narrow the timing margin of the circuitry.
An object of the present invention is to provide a constant-current generator whose supply current does not fluctuate even when a ground voltage VSS or a power supply voltage VDD has shifted.
Another object of the present invention is to provide a differential amplifier whose amplifying speed does not fluctuate even when a ground voltage VSS or a power supply voltage VDD has shifted.
Still another object of the present invention is to provide a semiconductor integrated circuit which includes a differential amplifier free from the fluctuation of the amplifying speed.
According to one of the aspects of the constant-current generator in the present invention, the generator comprises a bias transistor whose drain and gate are connected to each other, and an outputting transistor. The threshold voltage of the outputting transistor is smaller than that of the bias transistor. The outputting transistor has the same source voltage and the same gate voltage as those of the bias transistor. Therefore, the gate-to-source voltages of the outputting transistor and the bias transistor are always kept equal. On the other hand, the drain-to-source current of the outputting transistor becomes larger than that of the bias transistor in accordance with the difference between the threshold voltages of the outputting transistor and the bias transistor. Accordingly, the outputting transistor can output a stable drain-to-source current even when the drain voltage of the bias transistor has shifted to lower the gate-to-source voltage thereof.
According to another aspect of the constant-current generator in the present invention, the drain of the bias transistor is connected to a voltage generator. The voltage generator supplies a predetermined voltage to the drain of the bias transistor so as to set the drain-to-source voltage of the bias transistor larger than the threshold voltage thereof. Therefore, the drain voltage of the bias transistor approaches the source voltage thereof. Accordingly, the bias transistor is less affected by the shifting in the power source voltage.
By way of example, in a case where the bias transistor is a pMOS transistor, it is less affected by the shifting in a ground voltage. Since the bias transistor is in diode connection, it is also less affected by the shifting in the power source voltage. On the other hand, in a case where the bias transistor is an nMOS transistor, it is less affected by the shifting in the power source voltage. As a result, the outputting transistor can output a constant drain-to-source current in spite of the shifting in the power source voltage.
According to still another aspect of the constant-current generator in the present invention, the drain-to-source voltage of the bias transistor is easily generated by using a resistor.
According to yet another aspect of the constant-current generator in the present invention, a voltage controlling unit prevents the drain voltage of the bias transistor from shifting due to the shifting in the power source voltage. Therefore, the drain voltage of the bias transistor is held at a predetermined value without being affected by the shifting in the power source voltage. As a result, the outputting transistor can output the constant current irrespective of the shifting in the power source voltage.
According to yet another aspect of the constant-current generator in the present invention, the generator comprises a bias transistor whose drain and gate are connected to each other, an outputting transistor, and a voltage generator connected to the drain of the bias transistor. The outputting transistor has the same source voltage and the same gate voltage as those of the bias transistor. The voltage generator supplies a predetermined voltage to the drain of the bias transistor so as to set the drain-to-source voltage of the bias transistor larger than the threshold voltage thereof. Further, the voltage controlling unit of the voltage generator prevents the drain voltage of the bias transistor from shifting due to the shifting in the power source voltage. Therefore, the drain voltage of the bias transistor is held at a predetermined value without being affected by the shifting in the power source voltage. As a result, the outputting transistor can output a constant drain-to-source current irrespective of the shifting in the power source voltage.
According to one of the aspects of the differential amplifier in the present invention, a supply current from a constant-current generator is always kept constant irrespective of the shifting in the power source voltage, so that the amplifying speed of signals differentially inputted can always be kept constant, thereby to prevent the output timing of the amplified signal from shifting.
According to one of the aspects of the semiconductor integrated circuit in the present invention, the output timing of a signal amplified by a differential amplifier is held constant so that the timing margin of circuit is prevented from narrowing.